High Speed Design Made Easy Seminars

Technology, Topology & Termination

The Australian Microelectronics Centre in conjunction with In-Circuit Design Pty Ltd is presenting a series of free Lunch and Learn Seminars on High Speed PCB Design Made Easy in Brisbane this year.

The first in the series of seminars - Signal Integrity and DDR Design was held on the 28th of April 2006 and due to its unprecedented success the next seminar - Technology, Topology & Termination is planned for the 31st of May 2006.

This seminar will focus on the Fundamentals of High Speed Design:

1. TECHNOLOGY
Advances in Integrated Circuit manufacturing enable smaller and smaller dies on chips. Smaller dies means faster edge rates. Faster edge rates mean reflections and signal quality issues. So, even when the IC package hasn't changed and your clock speed hasn't changed there is still a problem for legacy designs and redesigns of your product.

2. TOPOLOGY
To avoid signal quality and timing problems, and to minimize manufacturing cost, thorough topology analysis is critical to successful high speed design. The bulk of this analysis can be done in the pre-layout stage where the type of topology can be selected based on design constraints.

3. TERMINATION
The optimal termination style should be selected for signal integrity, timing and EMC. The transmission line characteristic impedance can be matched to the source using a variety of termination styles - which is the best?

The goal of this seminar is to proactively eliminate signal transmission and Electromagnetic Compliancy problems, frequently encountered when implementing high speed designs, earlier in the process.

* LOCATION AND DATE *

Wednesday May the 31st, 12noon - 2pm
Australian Microelectronics Centre
Brisbane Technology Park
Cnr Logan & Miles Platting Rds
Eight Mile Plains, Qld 4113