High Speed Design Made Easy Seminars

Signal Integrity & DDR Design

We are presenting a series of free Seminars in Brisbane, Sydney, Melbourne and Adelaide on the latest technologies in High Speed PCB Design. These seminars are proudly supported by the Australian Microelectronics Centre, In-Circuit Design and Mentor Graphics.

The first in the series of seminars - Signal Integrity and DDR Design - enables Hardware Engineers and PCB Designers to quickly develop a DDR memory solution, making tradeoffs between terminations, minimum and maximum routing constraints, and loading in order to meet the signal integrity and timing requirements.

Double Data Rate (DDR) memory is today commonly used in Computers, Networking, Telecommunications, Consumer Electronics, Military, and Automotive applications. This seminar identifies the issues associated with designing products using DDR SDRAM and presents solutions to the design constraints.

* SEMINAR OUTLINE *

* Overview of the High Speed Design Made Easy Seminar Series
* DDR Technology overview
* Why it's important
* Who's using it
* Specification details
* Design issues
* Simulation
* Constraints

The goal of this seminar is to proactively eliminate signal transmission problems, frequently encountered when implementing these types of technologies into a design, earlier in the process. For engineering teams experiencing these challenges and looking for a systematic way to effectively implement DDR SDRAM design methodology, this seminar will demystify the process.

* LOCATIONS & DATES *

SYDNEY - Tuesday April 4th, 6 - 8pm
The Ranch Hotel
Willis Room
Cnr Epping & Herring Rds
Eastwood, NSW 2122

MELBOURNE - Wednesday April 5th, 6 - 8pm
The Matthew Flinders Taverner
State Room
667 Warrigal Rd
Chadstone, VIC 3148

BRISBANE - Friday April 28th, 12noon - 2pm
Australian Microelectronics Centre
Brisbane Technology Park
Cnr Logan & Miles Platting Rds
Eight Mile Plains, Qld 4113

ADELAIDE - TBA
Please register your interest and you will be notified of the venue and date.